ConnClark

Embedded Computer Designer, Circuit Board Designer, RF Layout Specialist. Porting the Linux to custom PPC boards since Kernel 2.2 current job: Senior Engineering Technician at Manufacturing Services Inc. http:www.njc.com

IBM takes a que from Oreo and double stuffs power 7+ chips

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Sep 052012

Timothy Prickett Morgan over at the Register Has a nice article on IBM doubling up processors to fit into a single socket. In some servers this may push the limits of the number of thread Linux can handle so expect patches to push this up further in the future. The article also has lots of other juicy details on the Power 7+.

I wish they would make one that I could drop in an athlon socket. I would rewrite my BIOS in a heart beat.

of interest… Nasa’s Curiosity rover is PowerPC based. It has two identical computers using the RAD750 CPU . Each computer has 256K of EEPROM, 256MB of DRAM, and 2GB of flash.  Unfortunately it uses VxWorks which leaves less than 75% of its CPU time for its autonomy software according to Wikipedia.

IBM to give each core 10MB of L3 cache (80MB total) on Power 7+ and more .

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Jul 162012

Author Timothy Prickett Morgan over at the wonderful site The Register has saved us from doing a lot of work by doing some intelligence analysis of IBM’s roadmaps. Highlights include a die shrink to 32nm, 80MB shared L3 cache, cryptographic accelerator, speed bumps, POWER 8 speculation, and pretty pictures.

While all of this will allow us to run vi faster, its not all a bed of roses. The increased cache size will reduce data stalls thus reduce the effectiveness of multithreading which relies on stalls to give it time to work. You can’t have it all.

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